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Re: draft-mannie-ccamp-gmpls-lbm-tdm-00.txt



Maarten,

I think also that it is written at the beginning of the 
corresponding section:

"This section is for further study but the principles 
could be based on the following ideas:" 

You wrote:
"I am intriged by this statement, and hope you are able 
to explain how this would be realised in a real SDH/SONET 
equipment and network."

I think this is one of the main purpose of this section 
open the discussion.

So i really appreciate your collaboration to go further
with this idea, let's discuss it and try to completely
specify how such process can be achieve by limiting the
disruption to the one achievable using other methods.

Thanks,
- dimitri.

Maarten Vissers wrote:
> 
> Eric, Dimitri,
> 
> You write in your document
> 
>   " For instance, a received SDH STM-64 frame can contain a VC-4-4c,
>    while a next frame can contain a VC-4-16c starting at the same
>    place as the VC-4-4c and thus occupying the same first VC-4
>    spaces. This process is not service impacting or disruptive. "
> 
> I am intriged by this statement, and hope you are able to explain how this would
> be realised in a real SDH/SONET equipment and network.
> 
> To me this looks very service impacting and disruptive.
> E.g. according to G.783, 75% of the VC-4-16c received will not be passed through
> while a series of AU3dLOP, AU4dLOP and/or AU4-4cdLOP will be detected and AIS is
> inserted.
> 
> Only if you have a modified AU pointer processor which is adaptive to the
> incoming signal structure you will not get any defects detected and AIS
> inserted; i.e. you can do this only if you have set up an AUG-N/STSG-N
> connection. In this AUG-N case you haven't specified the specific substructure,
> and don't need to do this. This is controlled by the user equipment, which will
> not be able to use the connection while e.g. circuit packs in the equipment are
> changed, or switches are made and pointer processors are reprovisioned.
> 
> Regards,
> 
> Maarten
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