Re: [RRG] Tunnel fragmentation/reassembly for RRG map-and-encaps architectures

[Yakov Rekhter <yakov@juniper.net>]

Dino,

> >>> Dino Farinacci wrote:
> >>>>> P.S. Since the ITR/ETR use caches, and reactively populate the
> >>>>> caches, IMHO, it's a step backwards, from CEF to pre-CEF bad-old-
> >>>>> days. (Sorry. Old wounds still ache from time to time :-). Not so
> >>>>> old if you include MSFC's...)
> >>>>
> >>>> We are not talking about the same scale. I can sell you a 10
> >>>> million entry cache, but you probably won't buy it.  ;-)
> >>>>
> >>> MacBook w/2GB running quagga - already have one, thanks. :-) :-)
> >>
> >> We are not talking about the same sort of products either.  ;-) If
> >> this needs to go fast, the MacBook memory won't run at 40-100G.
> >
> > For the purpose of this discussion we need to look separately at
> > the memory used by the control plane and the memory used by the
> > data plane. Your arguments that "the MacBook memory won't run at
> > 40-100G" may be relevant in the context of the memory used by the
> > data plane, but is *totally irrelevant* in the context of the memory
> > used by the control plane.
> 
> Yes, agree. That is what I implied since control-plane memory won't  
> have to run at speeds 40-100G.

Since the control plane memory does not seem to be a bottleneck, 
why do we need caches in the control plane ?

Yakov.

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