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Re: [RRG] Tunnel fragmentation/reassembly for RRG map-and-encaps architectures
Since the control plane memory does not seem to be a bottleneck,
why do we need caches in the control plane ?
The control plane memory could be a bottleneck and lack capacity for
10^9 entries. But granted, the LISP-ALT database (extended to carry
mapping entries which it does not do now) could be stored in control-
plane memory only and if you were doing software switching you could
use this larger database for forwarding and not a cache.
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