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Re: [RRG] Tunnel fragmentation/reassembly for RRG map-and-encaps architectures



On 7 jan 2008, at 19:37, Dino Farinacci wrote:

Since the control plane memory does not seem to be a bottleneck,
why do we need caches in the control plane ?

The control plane memory could be a bottleneck and lack capacity for 10^9 entries.

Since we have no upper limit on the number of EID prefixes = RIB entries, it's impossible to say what will not be a bottleneck. More practically, with BGP the RIB is some multiple of the FIB, but assuming that multiple stays within a reasonable range, the relationship is linear. As long as every destination in the RIB needs to go in the FIB (= no caching) the control plane probably won't be a bottleneck as long as we can afford the data plane.

However, what we really want is to avoid having to build a bigger box any time the number of EID prefixes increases. What we need is something that allows us to split the used EID space (not necessarily the possible EID space) into more or less equal parts that can be processed on separate small and affordable boxes.

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