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Re: [RRG] Tunnel fragmentation/reassembly for RRG map-and-encaps architectures



Iljitsch van Beijnum wrote:
On 7 jan 2008, at 19:37, Dino Farinacci wrote:

Since the control plane memory does not seem to be a bottleneck,
why do we need caches in the control plane ?

The control plane memory could be a bottleneck and lack capacity for 10^9 entries.

Since we have no upper limit on the number of EID prefixes = RIB entries, it's impossible to say what will not be a bottleneck.

Why do you say that? We have a population limit, if nothing else. Perhaps things won't scale if birds start having IP addresses...


Eliot

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